Tech-AI 芯片架构

Position Overview The AI Chip Architect will be responsible for defining and designing next‑generation AI computing architectures, including accelerator architecture, memory subsystem design, and system‑level performance optimization. This role requires deep technical expertise in AI workloads, chip architecture, and hardware–software co‑design, enabling the development of high‑performance, low‑power AI processors for edge, cloud, or consumer devices. Key Responsibilities Lead the architecture definition of AI accelerators, including compute units, dataflow, memory hierarchy, interconnect, and scheduling mechanisms. Analyze AI workloads (CNN, Transformer, LLM, diffusion models, etc.) to guide architecture decisions and performance optimization. Design and evaluate micro‑architecture components such as MAC arrays, systolic arrays, vector units, tensor cores, and custom compute engines. Define memory subsystem architecture, including SRAM/DRAM hierarchy, cache design, bandwidth planning, and data reuse strategies. Conduct system‑level modeling and performance simulation to evaluate throughput, latency, power consumption, and area trade‑offs. Collaborate with hardware, software, compiler, and algorithm teams to ensure optimal hardware–software co‑design. Participate in RTL review, verification planning, and bring‑up support to ensure architecture correctness and performance realization. Track industry trends in AI hardware, emerging workloads, and semiconductor technologies to drive next‑generation architecture innovation. Support customer requirements analysis and provide technical guidance for product definition and roadmap planning. Minimum Qualifications Bachelor’s degree or above in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, or related fields. 5+ years of experience in chip architecture, AI accelerator design, or high‑performance computing architecture. Strong understanding of AI/ML workloads, including CNN, RNN, Transformer, LLM, or other deep learning models. Solid knowledge of computer architecture fundamentals: pipelines, cache, memory hierarchy, interconnect, parallel computing. Experience with architecture modeling tools (e.g., SystemC, Python‑based simulators, gem5, custom simulators). Familiarity with RTL design and verification flows (Verilog/VHDL/SystemVerilog). Strong analytical and problem‑solving skills with the ability to evaluate performance, power, and area trade‑offs. Ability to collaborate across hardware, software, and algorithm teams.

职位描述

Kathleen Li